Fault-tolerant embedding of quantum circuits on hardware architectures via swap gates

by Chiew Shao Hen

In this blog post, we discuss our recent work [1], which proposes a protocol that enables quantum circuits to preserve their fault-tolerant properties when implemented on connectivity-constrained devices. This allows us to fault-tolerantly embed error-correction codes, such as the surface code, onto different devices, facilitating their implementation on near-term quantum devices featuring local connectivities.

Introduction — error correction in quantum devices

Quantum error correction (QEC) is an essential component for accurate quantum computation at scale. As real quantum computers are inherently noisy, implementations of QEC protocols are themselves subjected to faults and are thus designed with strict error propagation properties to ensure their fault-tolerance. Because of this, their implementations are also extremely sensitive to architectural aspects of the quantum device, such as their connectivity/topology, which restricts possible multi-qubit gates between qubits in the device.

Fig.1: The heavy-hexagonal (left) and square (right) lattices, featured respectively in IBM’s and Google’s quantum devices based on superconducting qubits. Nodes represent qubits, while edges represent possible entangling gates between qubits.

In general, one way to overcome device-connectivity limitations is to insert SWAP gates into the circuit, each having the effect of exchanging the positions of a pair of qubits. In this way, an arbitrary circuit, which we call the abstract circuit, can be transformed into one that respects the device connectivity. The problem of finding sequences of SWAP gates — which we call routing schedules — that carry out this transformation is known as qubit routing, and we refer to the output circuit as the routed circuit.

However, there is a risk here that we may be solving one problem only to create another. Fault-tolerant quantum error-correction (FTQEC) circuits are carefully designed to ensure that errors behave in controllable ways and cannot spread in such a manner as to make them uncorrectable. If a circuit that is originally fault-tolerant must be subject to qubit routing, resulting in a new circuit with potentially different ways for errors to propagate, is fault tolerance lost? This is the question that we set out to investigate in our work.

With these considerations in mind, we propose a strategy for performing routing that preserves the fault-tolerance of the underlying abstract circuit, thereby relaxing constraints on FTQEC set by device topologies.

Error-pattern-preserving routing

Intuitively, if we could find routed circuits where errors behave and propagate similarly to the abstract circuit, the routed circuit could inherit the fault-tolerance of the abstract circuit. More formally, in our work, we analyze the set of possible error-patterns — the spatio-temporal distribution of errors arising from faults across the circuit — that can arise in the routed circuit. The routed circuit is said to be error-pattern-preserving (EPP) if its error-patterns are identical to those arising in the abstract circuit.

A core result of our work is showing that routing schedules can be guaranteed to be EPP under certain conditions. Furthermore, we find that existing routing algorithms can be easily adapted to search for EPP routing schedules simply by building these conditions into the search. Given only the connectivities of the abstract circuit and the device, we can, therefore, output a routed circuit that preserves any underlying fault-tolerance properties of the abstract circuit.

Embedding the surface code

As a direct application of our method, we embed the syndrome extraction (SE) circuit of the rotated planar surface code — typically implemented on a square lattice — onto hardware with a heavy-hexagonal-lattice connectivity (see Fig. 1 (left) above), which is featured in IBM’s superconducting-qubit-based quantum computers. We consider the task of protecting physical qubits against noise over time using the surface code.

To recap the standard rotated planar surface code, its SE circuit (per cycle) involves four layers of CNOT gates between neighbouring qubits. It can be executed directly on a device with a square-grid topology (see Fig. 1 (right) above). For instance, focusing on individual qubits, the sub-circuits take the following forms:

The ancilla qubits are then repeatedly measured over several cycles of the above circuit, whose results allow us to infer and correct errors that have occurred. A classical decoding algorithm is also involved in the error inference process.

Our workflow to embed the above circuit onto the heavy-hexagonal lattice is the following:

1. Given the SE circuit and device topology, we use a classical search algorithm to output an EPP routing schedule.
2. We modify the decoding algorithm accordingly based on the form of the resulting EPP routing schedule and the form of the underlying abstract circuit.
3. We perform simulations of the routed circuits under a full-circuit noise model, verifying the fault tolerance of the EPP-routed circuit.

The resulting EPP routing schedule found by the search algorithm consists of 5 SWAP layers on top of the 4 existing CNOT layers. Because SWAP gates have the action of permuting pairs of qubits, we can also visualize the EPP-routing schedule via an animation such as the following:

Animation illustrating the action of a 5-SWAP layer EPP routing schedule over 2 cycles. Qubits that carry computational information (represented by black and coloured circles), embedded onto a heavy-hexagonal lattice, are synchronously transported by SWAP gates. Qubits that are adjacent to one another are then able to interact with one another via CNOT gates (coloured lines during CNOT timesteps).

To understand the embedding procedure's impact on the surface code's performance and verify its fault tolerance, we simulate both the embedded circuits and the un-embedded abstract circuit (i.e. the surface code executed on a square grid) under noisy conditions and compare their performances.

To analyze our results, we plot the curves of the logical error probabilities pL against the physical error probabilities of the two circuits together. Consistent with our theoretical arguments, the curves for the embedded circuit coincide almost perfectly with those of the abstract circuit if they are shifted horizontally. Thus, we introduce and plot against the effective physical error probability p_eff = cp instead, where c is the shift, and p is the physical error probability:

With c = 3.63, we observe excellent agreement between the two sets of curves; intuitively, this means that the routed circuit behaves like a noisier version of the abstract circuit, with the higher probability of error contributed by the additional SWAP operations. That the gradients of the lines — reliant on the circuit’s fault-tolerance properties — for the abstract and embedded circuits match well indicate the preservation of fault-tolerance. The threshold, the error probability below which error correction is beneficial, also deteriorates by the same factor c in the embedded circuit.

Analysing other device connectivities yields similar conclusions. An embedding of the same circuit on the hexagonal lattice yields a very similar plot, but with c = 1.25. Our technique can be applied to any device connectivity and any quantum circuit. Furthermore, the degree of deterioration can generally be estimated theoretically by deriving an effective noise model relating the embedded circuit to the abstract one.

Conclusion

In conclusion, we have proposed a general strategy to fault-tolerantly embed quantum circuits in connectivity-constrained devices. The central elements of our work consist of introducing and proving the fault-tolerance of EPP routing schedules and introducing methods to systematically obtain them under general conditions.

Our results lead to several significant consequences. Firstly, our approach is directly compatible with any device connectivity and quantum circuit. This opens up the possibility of implementing and testing QEC circuits on different devices, which is particularly relevant on the majority of current scalable quantum hardware architectures featuring geometrically local connectivities. Compared to existing methods, its generality provides a flexible route to implementing arbitrary circuits on hardware, including protocols that implement logical operations, state preparation, and more.

Secondly, applied to QEC circuits, our approach can result in embeddings that yield tolerable performance deteriorations, rendering them viable in near-term devices available today. As shown in the surface code examples above, the relatively small deterioration c suggests that the increase in error rates introduced by our approach will not present a major obstacle for near-term implementations.

Finally, from a broader perspective, our results yield new insights on the relationship between fault-tolerance and device-implementation details. By studying the properties and characteristics of EPP routing schedules in their own right, our results pave the way to new theoretical and practical results, which can motivate better architectures of quantum computers and QEC protocols.

References

[1] : Fault-tolerant embedding of quantum circuits on hardware architectures via swap gates. Shao-Hen Chiew, Ezequiel Ignacio Rodriguez Chiacchio, Vishal Sharma, Jing Hao Chai, Hui Khoon Ng. arXiv (2024).